Preliminary Information
Local Output Clock Control
The FMIC provides four output clocks which are
always driven off of the device. The FRAME output
clock has a duty cycle and period equal to the MVIP
F0 signal. The CLK2 and CLK4 output clocks are
identical to the MVIP C2 and C4 clocks, respectively.
The CLK8 output provides a 8.192MHz clock. The
frame pulse and output clocks may be used to
provide framing and clocking signals to serial
interfaces other than ST-BUS, such as, GCI bus.
Timing diagrams and parameters are provided in
Figures 19 and 20 along with the associated table.
The local output clock control register is defined in
Table 11 - “Local Clock Control (LOC_CLK)
Register”. The register allows the user to program
the polarity of the four local output clocks. In
addition, the register contains four read-only bits
which indicate the logic levels on EX_8KA, EX_8KB,
DACK0 and DACK1 input pins of the device.
Local Serial Interface
The local serial interface is implemented on 4 input
pins LDI[0:3] and four output pins LDO[0:3]. It can be
programmed in one of four different configurations by
setting the appropriate bits in the SER_MODE
register (refer to Figure 7 - “Serial Mode
(SER_MODE) Register” ).
In serial configuration one, the data rate is set to
2Mb/s. Each input stream is associated with a serial
input pin and each serial output stream is associated
with a serial output pin. There are 32 channels per
pin.
In serial configuration two, the data rate is set to
4Mb/s. Local streams 0 and 1 are multiplexed onto
input and output pins LDI[0] and LDO[0] and streams
2 and 3 are multiplexed onto input and output pins
LDI[2] and LDO[2]. There are 64 channels per pin
and the streams are multiplexed onto the pins as
shown in Table 12 - “SER_CNFG bits (control
configuration of local serial streams)” .
In serial configuration three, the data rate is set to
8Mb/s. All four local streams are multiplexed onto
pins LDI[0] and LDO[0]. There are 128 channels per
pin and the streams are multiplexed onto the pins as
shown in Table 12 - “SER_CNFG bits (control
configuration of local serial streams)” .
In serial configuration four, the data rate is set to
2Mb/s for streams 0 and 1 and 4Mb/s for streams 2
and 3. Streams 0 and 1 are associated with serial
pins LDI/O[0] and LDI/O[1], respectively. Streams 2
and 3 are multiplexed onto pin LDI[2] and LDO[2].
The streams are multiplexed onto the pins as shown
in Table 12 - “SER_CNFG bits (control configuration
of local serial streams)” .
Programmable Framing Signals
MT90810
The FMIC provides two groups of independently
programmable output framing signals:
FGA[0:11] group A output framing signals are
programmed
by
frame
start
register
A
(FRMA_STRT) and frame mode register A
(FRMA_MODE). FGB[0:11] group B output framing
signals are programmed by frame start register B
(FRMB_STRT) and frame mode register B
(FRMB_MODE).
The framing signals may be used to drive serial
buses interfaces other than ST-BUS.
The functional characteristics of a group of framing
output signals is controlled by MODE bits in the
frame mode register. Table 13 - “Frame Group Mode
bits” defines the various modes.
In mode 0, the frame group output depends on the
status of bits in the frame start and frame mode
registers. The values of the bits in frame start
register x (x is either A for group A or B for group B)
are driven out on pins FGx[0:7] and the values of bits
0 to 3 in frame mode register x are driven out on pins
FGx[8:11]. This mode is selected after device reset
when all bits in both registers are cleared.
In mode 1, the first four outputs of the frame group
FGx[0:3] are available for programmed output as in
mode 0. The other 8 outputs of each frame group are
available as output drive enables for the MVIP DSI/
DSO channels within the streams. FGA4 to FGA11
outputs correspond to output drive enables for the
MVIP DSo channels within streams 0 to 7,
respectively. For example, if only two DSo channels,
0 and 2 on stream 0, are enabled then the
corresponding channels 0 and 2 on FGA4 will be
pulled low and the remaining channels will be left
high. Similarly, FGB4 to FGB11 outputs correspond
to output drive enables for the MVIP DSi channels
within streams 0 to 7, respectively.
In mode 2, frame groups A&B are programmed as
output framing pulses for use with the local serial
data streams (refer to Figure 16 - “Frame Pulse
Timing for Mode 2” for further details). The position
of the first framing signal in a group is determined by
an 11 bit quantity. The quantity is the FMIC state
number (the number of 16MHz clock cycles during
one frame) minus one. The lower eight bits of this
quantity are located in the frame start register, and
the upper three bits are located in the frame mode
register.The width of the framing signal is determined
by the state of the FRM_TYPE bit in the frame mode
register and can be either a single bit cell time or 8
bit cell times. All framing signals in the same group
(A or B) follow each other sequentially, that is, the
first FGx[0] is asserted then exactly 8 bit cell times
later FGx[1] is asserted and so on until the last
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