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MT9079 参数 Datasheet PDF下载

MT9079图片预览
型号: MT9079
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS⑩系列高级控制器E1 [CMOS ST-BUS? FAMILY Advanced Controller for E1]
分类和应用: 控制器
文件页数/大小: 54 页 / 569 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9079  
Common Channel Signalling Interface  
The MT9079 Transparent Mode  
Figure 14 shows how to interface DSTi and DSTo  
time slot 16 to the MC68302 for the control of  
Common Channel Signalling (CCS) data. As can be  
seen in the timing diagram, the MT8980D CSTo  
signal must be programmed to go high during the bit  
position just before time slot 16 (i.e., time slot 15, bit  
0). This will enable the NMSI1 pins for one time slot  
(eight C2 cycles) when the NMSI1 port is operated in  
PCM mode. The STo stream of the MT8980D must  
also be programmed to be high impedance during  
time slot 16. C2 is used to clock data into and out of  
the NMSI1 port.  
Figure 15 illustrates an application in which the  
MT9079 transparent mode can be used. That is, a  
digital cross-connect multiplexer that switches  
complete PCM 30 trunks and does not require time  
slot switching. It should be noted that any MT9079  
devices that transport time slot switched data must  
operate in termination mode otherwise, the CRC-4  
remainder will be in error.  
In transparent mode the complete PCM 30 data  
stream will pass through the MT9079 except for the  
data link (S of the NFAS - 4kbit/sec. maintenance  
a4  
channel). The CRC-4 remainder will not be  
generated by the transmit section of the MT9079, but  
the CRC-4 remainder bits received on DSTi will be  
modified to reflect the new data link bits. This has the  
advantage that any CRC-4 errors that occur on the  
It should be noted that the DS signal of the MC68302  
must be inverted to interface to the MT8980D. Also,  
DTACK must be connected to the MT8980D DTA and  
pulled-up with a 909 ohms resistor.  
Digital Cross-Connect Matrix  
MT8980D  
MT8980D  
MT9079  
MT9079  
STi0  
STo0  
DSTo  
TxA  
DSTo  
DSTi  
TxA  
TxB  
TxB  
DSTi  
Switch 0,0  
Switch 0,M  
To Line  
Interface  
To Line  
Interface  
C4i/C2i  
C4i/C2i  
C4  
C4  
RxA  
RxB  
RxA  
RxB  
E2i  
m+1 Frame  
Delay  
E2i  
TxMF  
RxMF  
RxMF  
TxMF  
MT8980D  
MT8980D  
To Data Link  
Controller  
To Data Link  
Controller  
Switch n,0  
Switch n,M  
Figure 15 - PCM-30 (E1) Trunk Cross-Connect using the MT9079 Transparent Mode  
C4  
C2  
MT9079  
Manchester Encoder  
Transmit Fibre Interface  
DSTi  
DSTo  
CLKi  
Tx+  
Tx+  
C4i/C2i  
Transmit Fibre  
Receive Fibre  
NRZ  
NRZ  
TxA  
TxB  
Datai  
Tx-  
Tx-  
Manchester Decoder  
Receive Fibre Interface  
Data0  
RxA  
RxB  
E2i  
CODEi  
RxCLK  
RxData  
Figure 16 - MT9079 Fibre Interface Circuit  
4-279  
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