Preliminary Information
MT9076
There are two maskable interrupts associated with the frame alignment signal error measurement. FERI (page
01H, address 1CH) is initiated when the least significant bit of the errored frame alignment signal counter
toggles, and FERRO (page 01H, address 1DH) is initiated when the counter changes from FFH to 00H.
13.5
E-bit Counter (EC15-0)
E-bit errors are counted by the MT9076 in order to support compliance with ITU-T requirements. This sixteen
bit counter is located on page 04H, addresses 14H and 15H respectively. It is incremented by single error
events, with a maximum rate of twice per CRC-4 multiframe.
There are two maskable interrupts associated with the E-bit error measurement. EBI (page 1, address 1CH) is
initiated when the least significant bit of the counter toggles, and FEBEO (page 01H, address 1DH) is initiated
when the counter overflows.
13.6
Line Code Violation Error Counter (LCV15-LCV0)
If the control bit EXZ (page 1 address 12H bit 5) is set low, the line code violation error counter will count
bipolar violations that are not part of HDB3 encoding. If the control bit EXZ (page 1 address 12H bit 5) is set
high, the line code violation error counter will count both bipolar violations that are not part of HDB3 encoding
and each occurance of excess zeros (more than 3 successive zeros in a received HDB3 encoded data stream
and more than 15 successive zeros in a non-HDB3 encoded stream). This counter LCV15-LCV0 is 16 bits long
(page 4H, addresses 16H and 17H) and is incremented once for every line code violation received. It should be
noted that when presetting or clearing the LCV error counter, the least significant LCV counter address should
be written to before the most significant location. This counter will suspend operation when terminal frame
synchronization is lost if the control bit OOFP is set (bit 2, address 1AH - Reset Control Word).
In E1 mode, there are two maskable interrupts associated with the line code violation error measurement. LCVI
(page 01H, address 1CH) is initiated when the l significant bit of the LCV error counter toggles. LCVO (page
01H, address 1DH) is initiated when the counter changes from FFFFH to 0000H.
13.7
CRC-4 Error Counter (CC15-0)
CRC-4 errors are counted by the MT9076 in order to support compliance with ITU-T requirements. This sixteen
bit counter is located on page 04H, addresses 18H and 19H in E1 mode. It is incremented by single error
events, which is a maximum rate of twice per CRC-4 multiframe.
There is a maskable interrupt associated with the CRC error measurement. CRCIM (page 01H, address 1CH)
is initiated when the least significant bit of the counter toggles, and CRCOM (page 01H, address 1DH) is
initiated when the counter overflows.
13.8
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS comparison; one for errors and one for time. Any errors that
are detected in the receive PRBS will increment the PRBS Error Rate Counter of page 04H, address 10H.
Writes to this counter will clear an 8 bit counter, PSM7-0 (page 01H, address 11H) which counts receive CRC
multiframes. A maskable PRBS counter overflow (PRBSO) interrupt (page 1, address 1DH) is associated with
this counter.
13.9
CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4 multiframes. It can be directly loaded via the microport. The
counter will also be automatically cleared in the event that the PRBS error counter is written to by the
microport. This counter is located on page 04H, address 11H.
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