Preliminary Information
MT9075B
Bit
Name
Functional Description
Bit
Name
Functional Description
Frame Abort/TX FIFO Underrun.
7-0
Ga,
This register is used with the
2
FA:
EOPD, Interrupt Register to mask out the
TEOP, interrupts that are not required by
EOPR, the microprocessor. Interrupts that
Txunder When Intsel bit of Control Register 2
is low, this bit is set to one when a
frame abort is received during pack-
et reception. It must be received af-
ter a minimum number of bits have
been received (26) otherwise it is ig-
nored.
TxFl,
FA:
are masked out will not produce an
IRQ; however, they will set the
Txunder, appropriate bit in the Interrupt
RxFf & Register. An interrupt is disabled
RxOvfl when the microprocessor writes a 0
When Intsel bit of Control Register
2 is one, this bit is set to one for a
TX FIFO underrun indication. If one
it indicates that a read by the
transmitter was attempted on an
empty Tx FIFO.
to a bit in this register. This register
is cleared on power reset.
(000000)
Table 90 - HDLC Interrupt Mask Register
(Pages 0BH & 0CH, Address 16H)
This bit is reset after a read.
1
0
RxFf
RX FIFO Full. This bit is set to one
when the RX FIFO is filled above
the selected full threshold level.
This bit is reset after a read.
Bit
Name
Functional Description
7
GA
Go-Ahead. Indicates a go-ahead
pattern was detected by the HDLC
receiver. This bit is reset after a
read.
RxOvfl RX FIFO Overflow. A one indicates
that the 128 byte RX FIFO
overflowed (i.e. an attempt to write
to a 128 byte full RX FIFO). The
HDLC will always disable the
receiver once the receive overflow
has been detected. The receiver
will be re-enabled upon detection of
the next flag, but will overflow again
unless the RX FIFO is read. This bit
is reset after a read.
6
EOPD End Of Packet Detect. This bit is
set to one when an end of packet
(EOP) byte was written into the RX
FIFO by the HDLC receiver. This
can be in the form of a flag, an abort
sequence or as an invalid packet.
This bit is reset after a read.
5
4
TEOP Transmit End Of Packet. This bit is
set to one when the transmitter has
finished sending the closing flag of a
packet or after a packet has been
aborted. This bit is reset after read.
Table 91 - HDLC Interrupt Status Register
(Page 0BH & 0CH, Address 17H)
EOPR End Of Packet Read. This bit is set
to one when the byte about to be
read from the RX FIFO is the last
byte of the packet. It is also set to
one if the Rx FIFO is read and there
is no data in it. This bit is reset after
a read.
Bit
Name
Functional Description
7 - 0 Crc15-8 The MSB byte of the CRC received
from the transmitter. These bits are
as the transmitter sent them; that is,
most significant bit first and
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
3
TxFL
TX FIFO Low. This bit is set to one
when the TX FIFO is emptied below
the selected low threshold level.
This bit is reset after a read.
Table 92 - Receive CRC MSB Register
(Pages 0BH & 0CH, Address 18H)
Table 91 - HDLC Interrupt Status Register
(Page 0BH & 0CH, Address 17H) (continued)
61
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