MT9075B
Preliminary Information
Bit
Name
Functional Description
Bit
Name
Functional Description
3, 2 Txstat2, Transmit Status. These bits
Txstat1 indicate the status of the TX FIFO
as follows:
7
Intsel
(0)
Interrupt Selection. When one, this
bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO
underrun (TXunder). When zero,
this interrupt will reflect a frame
abort (FA).
Txsta Txsta
TX FIFO Status
t2
t1
0
0
TX FIFO full up to
the selected status
level or more. See
Table 93.
6
5
Cycle When one, this bit will cause the
transmit byte count to cycle through
the value loaded into the Transmit
Byte Count Register.
(0)
The number of bytes
in the TX FIFO has
Tcrci
(0)
Transmit CRC Inhibited. When
one, this bit will inhibit transmission
of the CRC. That is, the transmitter
will not insert the computed CRC
onto the bit stream after seeing the
EOP tag byte. This is used in V.120
terminal adaptation for synchronous
protocol sensitive UI frames.
0
1
reached
exceeded
selected
or
the
interrupt
threshold level. See
Table 94.
1
1
0
1
TX FIFO empty.
4
Seven Seven Bits Address Recognition.
The number of bytes
in the TX FIFO is
When one, this bit will enable seven
bits of address recognition in the
first address byte. The received
address byte must have bit 0 equal
(0)
less
than
the
selected
interrupt
threshold level. See
Table 94.
to
1 which indicates a single
address byte is being received.
1, 0 Rxstat2, Receive Status. These bits
Rxstat1 indicate the status of the RX FIFO
as follows:
3
2
1
RSV
(0)
Reserved, must be zero for normal
operation.
Rxsta Rxsta
RX FIFO Status
RSV
(0)
Reserved, must be zero for normal
operation.
t2
t1
0
0
0
1
RX FIFO empty.
Rxfrst RX FIFO Reset. When one, the RX
FIFO will be reset. This causes the
receiver to be disabled until the next
reception of a flag. The status
register will identify the FIFO as
being empty. However, the actual
bit values in the RX FIFO will not be
reset.
(0)
The number of bytes
in the RX FIFO is
less
than
the
selected threshold
level. See Table 94.
1
1
0
1
RX FIFO full up to
the selected status
level or more. See
Table 93.
0
Txfrst TX FIFO Reset. When one, the TX
FIFO will be reset. The Status
Register will identify the FIFO as
being empty. This bit will be reset
when data is written to the TX FIFO.
However, the actual bit values of
data in the TX FIFO will not be
reset. It is cleared by the next write
to the TX FIFO.
(0)
The number of bytes
in the RX FIFO has
reached
exceeded
selected
or
the
interrupt
threshold level. See
Table 94.
Table 89 - HDLC Control Register 2
(Pages 0BH & 0CH, Address 15H)
Table 88 - HDLC Status Register
(Pages 0BH & 0CH, Address 14H)
60
MITEL [ MITEL NETWORKS CORPORATION ]
