Preliminary Information
MT9075B
Bit
Name
Functional Description
Bit
Name
Functional Description
Unused.
7 - 4
3
RSV
These bits are reserved.
7
---
RXclk This bit represents the receiver
clock generated after the RXEN
control bit is enabled, but before
zero deletion is considered.
6 - 4 RFD2 - 0 These bits select the Rx FIFO full
status level:
(000)
RFD2 RFD1 RFD0 Full Status
Level
2
1
TXclk This bit represents the transmit
clock generated after the TXEN
control bit is enabled, but before
zero insertion is considered.
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
0
0
48
Vcrc
This is the CRC recognition status
bit for the receiver. Data is clocked
into the register and then this bit is
monitored to see if comparison was
successful (bit will be one).
0
64
1
80
1
96
0
Vaddr This is the address recognition
status bit for the receiver. Data is
1
112
128
clocked
into
the
Address
1
Recognition Register and then this
bit is monitored to see if comparison
was successful (bit will be one).
3
---
Unused.
2 - 0 TFD2 - 0 These bits select the Tx HDLC
FIFO full status level:
(000)
Table 96 - HDLC Test Status Register
(Page 0BH & 0CH, Address 1CH)
TFD2 TFD1 TFD0 Full Status
Level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
48
64
80
96
112
128
Table 97 - HDLC Control Register 3
(Pages 0BH & 0CH, Address 1DH)
63
MITEL [ MITEL NETWORKS CORPORATION ]
