MT9075B
Preliminary Information
Bit
Name
Functional Description
Bit
Name
Functional Description
7 - 0 Crc7 - 0 The LSB byte of the CRC received
from the transmitter. These bits are
as the transmitter sent them; that is,
most significant bit first and
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
6
RTloop RT Loopback. When this bit is set
to one, receive to transmit HDLC
loopback will be activated. Receive
data, including end of packet
indication, but not including flags or
CRC, will be written to the TX FIFO
as well as the RX FIFO. When the
transmitter is enabled, this data will
be transmitted as though written by
the microprocessor. Both good and
bad packets will be looped back.
Receive to transmit loopback may
also be accomplished by reading
(0)
Table 93 - Receive CRC LSB Register
(Pages 0BH & 0CH, Address 19H)
the
RX
FIFO
using
the
Bit
Name
Functional Description
Transmit Byte Count
microprocessor and writing these
bytes, with appropriate tags, into the
TX FIFO.
7 - 0 Cnt7 - 0 The
Register. It is used to indicate the
length of the packet about to be
transmitted. When this register
reaches the count of one, the next
write to the Tx FIFO will be tagged
as an end of packet byte. The
counter decrements at the end of
the write to the Tx FIFO. If the Cycle
bit of Control Register 2 is set high,
the counter will cycle through the
programmed value continuously.
(0000
0000)
5
4
3
2
RSV
(0)
Reserved; must be set to 0 for
normal operation.
RSV
(0)
Reserved; must be set to 0 for
normal operation.
RSV
(0)
Reserved; must be set to 0 for
normal operation.
Ftst
(0)
FIFO Test. This bit when set to one
allows the writing to the RX FIFO
and reading of the TX FIFO through
the microprocessor to allow more
efficient testing of the FIFO status/
interrupt functionality. This is done
by making a TX FIFO write become
a RX FIFO write and a RX FIFO
read become a TX FIFO read. In
addition, EOP/FA and RQ8/RQ9 are
re-defined to be accessible (i.e. RX
write causes EOP/FA to go to RX
fifo input; TX read looks at output of
TX FIFO through RQ8/RQ9 bits).
Table 94 - Transmit Byte Count register
(Pages B & C, Address 1AH)
Bit
Name
Functional Description
7
HRST HDLC Reset. When this bit is set to
one, the HDLC will be reset. This is
similar to RESET being applied, the
only difference being that this bit will
not be reset automatically. This bit
can only be reset by writing a zero
twice to this location or applying
RESET.
(0000
0000)
1
0
RSV
(0)
Reserved; must be set to 0 for
normal operation.
Table 95 - HDLC Test Control Register
(Pages 0BH & 0CH, Address 1BH) (continued)
---
Unused.
Table 95 - HDLC Test Control Register
(Pages 0BH & 0CH, Address 1BH)
62
MITEL [ MITEL NETWORKS CORPORATION ]
