Preliminary Information
MT9075B
HDLC Control and Status (Page 0BH & 0CH)
Register
Address
Name
Control (Write/Verify)
Status (Read)
10H (Table 83)
11H (Table 84)
Address Recognition 1
Address Recognition 2
TX FIFO
---
---
Adr16-Adr10, A1en
Adr26-Adr20, A2en
Bit7-Bit0
12H (Table85)
& (Table 86)
RX FIFO
---
13H (Table 87)
14H (Table 88)
15H (Table 89)
16H (Table 90)
17H (Table 91)
HDLC Control 1
---
Adrec, RxEN, TxEN, EOP, FA, Mark-idle,
RSV, RSV
HDLC Status
Intgen, Idle-Chan, RQ9, RQ8, Txstat2,
Txstat1, Rxstat2, Rxstat1
HDLC Control 2
Interrupt Mask
---
---
---
Intsel, Cycle, Tcrci, Seven, RSV, RSV,
Rxfrst, Txfrst
Ga,
EOPD,
TEOP,
EOPR,
TxFl,
FA:Txunder, RxFf, RxOvfl
Interrupt Status
Ga, EOPD, TEOP,
EOPR,
TxFl,
FA:Txunder, RxFf, RxOvfl
18H (Table 92)
19H (Table 93)
1AH (Table 94)
1BH (Table 95)
---
Rx CRC MSB
Crc15-Crc8
---
Rx CRC LSB
Crc7-Crc0
TX byte count
Test Control
---
---
Cnt7-Cnt0
HRST, RTloop, RSV, RSV, RSV, Ftst, RSV,
Hloop
1CH (Table 96)
1DH (Table 97)
1EH (Table 98)
---
Test Status
RXclk, TXclk, Vcrc, Vaddr
RFD2-0, TFD2-0
HDLC Control 3
HDLC Control 4
---
---
RFFS2-0, TFLS2-0
Table 82 - HDLC 0 & 1 Control and Status (Pages 0BH & 0CH)
57
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