MT9075A
Preliminary Information
Pin Description (continued)
Pin #
Name
Description
PLCC MQFP
64
61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated 2.048
Mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 kHz. The transmit data link data
(TxDL) is clocked in on the rising edge of TxDLCLK. TxDLCLK can also be used to clock
DL data out of an external serial controller.
65
66
62
63
TxDL
Transmit Data Link (Input). An input serial stream of transmit data link data at 4, 8, 12,
16 or 20 kbit/s composed of 488ns-wide bit cells which are multiplexed into selected
national bits of the PCM 30 transmit signal.
BL/FR BusorLine/Freerun (Input). If this pin is set to high, the MT9075A is in the System Bus
or Line Synchronous mode depending on the BS/LS pin. If low, the MT9075A is in the
free run mode.
67
68
64
65
VDD
VSS
NC
Positive Power Supply (Input). Digital supply (+5V ± 5%).
Negative Power Supply (Input). Digital ground.
No Connection. Leave open for normal operation.
1-7,
25-31,
49-56,
75-82,
100
4-134
MITEL [ MITEL NETWORKS CORPORATION ]
