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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT9074  
Bit  
Name  
Functional Description  
Bit  
Name  
Functional Description  
1
RPSIG Serial Signaling Enable. If set  
low, the transmit signaling buffer  
for the equivalent DS1 channel will  
be sourced from the ST-BUS  
channel on CSTi associated with  
it. If set high the transmit signaling  
RAM must be programmed via the  
microport.  
7
TXMSG Transmit Message Mode. If high,  
the data contained in the Transmit  
Message Register (address 18H,  
page 1) is transmitted in the  
corresponding DS1 time slot. If  
zero, the data on DSTi is  
transmitted on the corresponding  
DS1 time slot.  
0
CC  
Clear Channel. When set high no  
robbed bit signaling is inserted in  
the equivalent transmit DS1  
channel. When set low robbed bit  
signaling is included in every 6th  
channel.  
6
PCI  
Per Channel Inversion. When set  
high the data for this channel  
sourced from DSTi is inverted  
before being transmit onto the  
equivalent DS1 channel; the data  
received from the incoming DS1  
channel is inverted before it  
emerges from DSTo.  
Table 75 - Per Time Slot Control Words  
(Pages 7 and 8) (T1)  
5
4
RTSL  
LTSL  
Remote Time Slot Loopback. If  
one, the corresponding DS1  
receive time slot is looped to the  
corresponding DS1 transmit time  
slot. This received time slot will  
also be present on DSTo. If zero,  
the loopback is disabled.  
Local Time Slot Loopback. If  
one, the corresponding transmit  
time slot is looped to the  
corresponding receive time slot.  
This transmit time slot will also be  
present on the transmit DS1  
stream. If zero, this loopback is  
disabled.  
3
TTST  
Transmit Test. If one, a test  
signal, either digital milliwatt (when  
control bit ADSEQ is one) or  
15  
PRBS (Z -1) (ADSEQ is zero),  
will be transmitted in the  
corresponding DS1 time slot. More  
than one time slot may be  
activated at once. If zero, the test  
signal will not be connected to the  
corresponding time slot.  
2
RTST  
Receive Test. If one, the  
corresponding DSTo time slot will  
be used for testing. If control bit  
ADSEQ is one, a digital milliwatt  
signal will be transmitted into the  
DSTo channel. If ADSEQ is zero,  
the receive channel will be  
15  
connected to the PRBS (2 - 1)  
detector.  
Table 75 - Per Time Slot Control Words  
(Pages 7 and 8) (T1)  
67  
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