Advance Information
MT9074
Per Channel Transmit Signalling (Pages 5 and 6) (T1)
Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit
Signalling Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 107 illustrates the mapping
between the addresses of these pages and the DS1 channel numbers. Control of these bits for any one
channel is through the processor or controller port when the Per Time Slot Control bit RPSIG bit is high. Table
72 describes bit allocation within each of these registers.
Page 5-6 Address:
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15
Equivalent DS1
channel
10 11 12 13 14 15 16
Page 6 Address:
0
1
2
3
4
5
6
7
8
x
9
x
10 11 12 13 14 15
Equivalent DS1
channel
17 18 19 20 21 22 23 24
x
x
x
x
x
x
Table 71 - Page 5, 6 Address Mapping to DS1 Channels (T1)
Bit
Name
Functional Description
7 - 4
3
- - -
Unused.
A(n)
Transmit Signalling Bits A for Channel n. Where signalling is enabled, these bits
are transmitted in bit position 8 of the 6th DS1 frame (within the 12 frame
superframe structure for D4 superframes and the 24 frame structure for ESF
superframes).
2
B(n)
Transmit Signalling Bits B for Channel n. Where signalling is enabled, these bits
are transmitted in bit position 8 of the 12th DS1 frame (within the 12 frame
superframe structure for D4 superframes and the 24 frame structure for ESF
superframes).
1
0
C(n)
D(n)
Transmit Signalling Bits C for Channel n. Where signalling is enabled, these bits
are transmitted in bit position 8 of the 18th DS1 frame within the 24 frame structure
for ESF superframes. In D4 mode these bits are unused.
Transmit Signalling Bits D for Channel n. Where signalling is enabled, these bits
are transmitted in bit position 8 of the 24th DS1 frame within the 24 frame structure
for ESF superframes. In D4 mode these bits are unused.
Table 72 - Transmit Channel Associated Signalling (T1) (Pages 5,6)
Serial per channel transmit signalling control through CSTi is selected when the Per Time Slot Control bit
RPSIG bit is low. Table 71 describes the bit allocation within each of the 24 active ST-BUS time slots of CSTi.
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