Advance Information
CMOS MT90732
The transmitter operates independently of the receiver,
unless the loop timing feature(LPT) is selected, when
the receive clock becomes the transmitted clock. In the
transmit direction, the terminal side bit-serial interface
consists of: data input signal (XSD), a clock input sig-
nal (XCK), and a framing pulse (XSF). The nibble-par-
allel interface consists of the following signals: a data
input signal having a nibble format (XNIB3 - XNIB0), a
clock input signal (XCK), a framing output pulse (XNF),
and a nibble output clock signal (XNC). The transmit
nibble clock (XNC) is stretched to accommodate the
framing pattern, service bit and BIP-4 times.
also controls the receive interface selection. When the
internal HDB3 Encoder Block is bypassed, the trans-
mit line interface consists of a data signal (TDL) and a
clock signal (TCKL). When the HDB3 encoder is
enabled, the transmit line interface consists of positive
(TP) and negative (TN) rail signals and a clock signal
(TCK).
A high placed on the microprocessor control lead
(MICRO) selects the microprocessor interface. All the
external control leads, except the loop timing (LPT),
receive AIS disable (DAIS), and the line interface con-
trol leads (NRZLINE) are disabled when the micropro-
cessor interface is selected.
MT90372 provides interface to service bits as defined
in G.7XX recommendations.The receive service bit
interface consists of: data output (ROD), clock output
(ROC), and framing pulse (ROF) output. The clock sig-
nal (ROC) is gapped and is provided for clocking out
the service bits. The service bit states are also written
into E2/E3F memory locations, which can be read by
the microprocessor. The transmitted service bits are
inserted into the frame format from either an external
interface or from memory map locations. The transmit
service bit interface consists of data input signal
(TOD), a clock output (TOC), and a framing pulse
(TOF) output.
The microprocessor interface consists of eight bidirec-
tional data and address leads (AD7 - AD0), along with
other microprocessor control leads, including a ready
(RDY) signal.
Typical Application
The E2/E3 Framer is used for wideband data
transport as shown in Figure 2. In the receive
direction, the E2/E3 Framer receives NRZ or dual rail
data from LIU, removes overhead bits and puts out
only the payload of the incoming signal to the
terminal. Overhead bits can be accessed through
microprocessor or by service bit interface. In the
transmit direction, the E2/E3 Framer receives data
generated from Data Source, adds framing pattern
and service bits and sends it out to LIU. The E2/E3
Framer handles wideband data at either 8448 or 34
368 Kb/s, and can optionally perform BIP-4 making
data transport more reliable.
To fix transmit time-base for the terminal payload multi-
plexer circuitry, while operating in the bit-serial mode,
the E2/E3F provides a transmit frame reference gener-
ator. The transmit frame reference generator accepts
an external 8.448 or 34.368 MHz clock signal (TCIN)
and produces a clock out signal (TCOUT), a framing
pulse (TFOUT), a clock gap signal (TCG), and a data
signal (TDOUT). The data signal consists of G.7XX
framing bits and zeros elsewhere.
The selection of the transmit line interface, dual rail or
NRZ, is controlled by the NRZLINE control lead, which
Line Side
Terminal Side
Rx
Line
E2/E3
Framer
Wideband
Interface
Data Sink/ Source
Unit
Tx
Overhead bit-I/O
Figure 2. Wideband Data Transport using E2/E3 Framer
5-21
MITEL [ MITEL NETWORKS CORPORATION ]
