Advance Information
many frames. The rate of change of the
±200ns
phase shift is limited to a maximum phase slope of
approximately 5ns/125us. This meets the Bellcore
GR-1244-CORE maximum phase slope requirement
of 7.6ns/125us (81ns/1.326ms).
Phase Lock Time
This is the time it takes the synchronizer to phase
lock to the input signal. Phase lock occurs when the
input signal and output signal are not changing in
phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is
affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
Although a short lock time is desirable, it is not
always possible to achieve due to other synchronizer
requirements. For instance, better jitter transfer
performance is achieved with a lower frequency loop
filter which increases lock time. And better (smaller)
phase slope performance (limiter) results in longer
lock times. The MT9041B loop filter and limiter were
optimized to meet the AT&T TR62411 jitter transfer
and phase slope requirements. Consequently, phase
lock time, which is not a standards requirement, may
be longer than in other applications. See AC
Electrical Characteristics - Performance for
maximum phase lock time.
MT9041B
Applications
This section contains MT9041B application specific
details for clock and crystal operation, reset
operation and power supply decoupling.
Master Clock
The MT9041B can use either a clock or crystal as
the master timing source.
In Freerun Mode, the frequency tolerance at the
clock outputs is identical to the frequency tolerance
of the source at the OSCi pin. For applications not
requiring an accurate Freerun Mode, tolerance of the
master timing source may be
±100ppm.
For
applications requiring an accurate Freerun Mode,
such as Bellcore GR-1244-CORE, the tolerance of
the master timing source must be no greater than
±32ppm.
Another consideration in determining the accuracy of
the master timing source is the desired capture
range. The sum of the accuracy of the master timing
source and the capture range of the MT9041B will
always equal
±230ppm.
For example, if the master
timing source is
±100ppm,
then the capture range
will be
±130ppm.
Clock Oscillator
- when selecting a Clock Oscillator,
numerous parameters must be considered. These
include absolute frequency, frequency change over
temperature, output rise and fall times, output levels
and duty cycle. See AC Electrical Characteristics.
MT9041B
MT9041B and Network Specifications
The MT9041B fully meets all applicable PLL
requirements (intrinsic jitter, jitter tolerance, jitter
transfer, frequency accuracy, capture range and
phase change slope) for the following specifications.
1. Bellcore GR-1244-CORE Issue 1, June 1995 for
Stratum 4 Enhanced and Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum
4 Enhanced and Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 4
Enhanced and Stratum 4
4. ETSI 300 011 (E1) April 1992 forSingle Access
and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
OSCi
+5V
+5V
20MHz OUT
GND
0.1uF
OSCo
No Connection
Figure 5 - Clock Oscillator Circuit
7
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