MT9041B
T1/E1 System Synchronizer
Advance Information
Features
•
Supports AT&T TR62411 and Bellcore
GR-1244-CORE Stratum 4 Enhanced and
Stratum 4 timing for DS1 Interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 Interfaces
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Provides C1.5, C2, C3, C4, C8 and C16 output
clock signals
Provides 3 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9 Hz
DS5059
ISSUE 3
Septemner 1999
Ordering Information
MT9041BP
28 Pin PLCC
-40 to +85
°C
•
•
•
•
•
Description
The MT9041B T1/E1 System Synchronizer contains
a digital phase-locked loop (DPLL), which provides
timing and synchronization signals for multitrunk T1
and E1 primary rate transmission links.
The MT9041B generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9041B is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE Stratum 4 Enhanced,
Stratum 4, and ETSI ETS 300 011. It will meet the
jitter tolerance, jitter transfer, intrinsic jitter, frequency
accuracy, capture range and phase change slope
requirements for these specifications.
Applications
•
•
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
VDD
VSS
OSCi
OSCo
C1.5o
REF
Phase
Detector
Loop
Filter
DCO
Output
Interface
Circuit
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Mode Select
Divider
MS
RST
FS1
FS2
Figure 1 - Functional Block Diagram
1
MITEL [ MITEL NETWORKS CORPORATION ]
