MT90220
7.6 External SRAM Register Description
Tables 61 to 65 describe the External SRAM registers.
Address (Hex):
Direct access
Reset Value (Hex):
292
Defines the external SRAM configuration
08
Bit #
Type
Description
7
6
R/W
R/W
R/W
R/W
R/W
Write a 1 to reset the receiver. 0 means no action.
Write a 1 to reset the transmitter. 0 means no action.
Reserved, write 0 for normal operation.
Write 00 for normal operation
5
4:3
2:0
These 3 bits define the size of the external receive memory:
101: 2 banks of 512K x 8 bits
100: 1 bank of 512K x 8 bits
011: 2 banks of 128K x 8 bits
010: 1bank of 128K x 8 bits
001: 2 banks of 32K x 8 bits
000: 1bank of 32K x 8 bits
Table 61 - SRAM Control Register
Address (Hex):
283
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
register
Reset Value (Hex):
00
Bit #
Type
Description
7:0
R/W
RX External SRAM Read/Write data register.
Table 62 - RX External SRAM Read/Write Data
Address (Hex):
291
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
register
Reset Value (Hex):
00
Bit #
Type
Description
7:0
R/W
RX External SRAM Read/Write Address bit 7:0.
Table 63 - RX External SRAM Read/Write Address 0
Address (Hex):
290
Synchronized access Set address before the transfer is initiated with the RX External SRAM Control
register
Reset Value (Hex):
00
Bit #
Type
Description
7:0
R/W
RX External SRAM Read/Write Address bit 15:8.
Table 64 - RX External SRAM Read/Write Address 1
60
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