MT90220
The IRQ enable bit of a counter is set, or reset, by
selecting the counter and writing to the appropriate
bit of the Counter Transfer Command register. The
value ’0x001010’ enables the counter IRQ and
’xxx00010’ disables (masks) it.
links. Each bit of this register corresponds to a link. A
’1’ in a bit position indicates that the associated link
is reporting an interrupt condition. For each bit in the
IRQ Master Status register, there is a corresponding
bit in the IRQ Master Enable register. When any IRQ
source is active and the corresponding Enable bit is
’1’, then the IRQ pin will go LOW (active).
6.2 Interrupt Block
The MT90220 can generate interrupts from many
sources. All interrupt sources can be enabled or
disabled. Write action is required to clear the source
of interrupt. Interrupts are grouped on a per link
basis, with six sub-categories for each link and two
special types for the IMA Group configuration. These
special interrupts are only present in the Link 0 IRQ
The IRQ Master Status register always reports the
current state of the source(s) of interrupt. It does not
latch the interrupt request(s); it only reports that one
or more bit(s) in one or more IRQ Link Status
register(s) is (are) set.
Status register. Refer to Figure 18 for
representation of the interrupt register hierarchy.
a
The bits that are read as active (’1’ value) are
cleared when the source of the interrupt is cleared or
when the corresponding bit(s) in the IRQ Link
Enable register(s) is (are) set to 0. Writing to or
reading from the IRQ Master Status register has no
effect on the level of the interrupt pin.
6.2.1 IRQ Master Status and IRQ Master Enable
Registers
There is a Master IRQ Status register that reports
interrupts generated by any event on any of the eight
Link 7
Link 6
Link 5
Link 4
Link 3
Link 2
Link 1
Link 0
1 UTOPIA
RX FIFO Overflow
S
T
A
T
U
S
4 UTOPIA
Counters
8 x IRQ
1 x IRQ
Master
Link
4 TX
Counters
Registers
Registers
4 RX
Counters
Link 7
E
S
T
A
T
U
S
N
A
B
L
0
Link UNI Overflow Status
LCD
S
T
A
T
U
S
E
N
A
B
L
LIF
LODS
IV
IRQ PIN
E
Link 0
New RX ICP
READY BIT/ICP CELL TIME *
E
IMA GRP CNTRS *
7
Frame
Pulse
UTOPIA IMA
Group Counters
E
N
A
B
L
S
T
A
T
U
S
Transfer
Done
E
S
T
A
T
U
S
S
T
A
T
U
S
E
N
A
B
L
1 UTOPIA
RX FIFO Overflow
4 UTOPIA
Counters
TX ICP Cell
Handler Register
E
IMA Group
OVERFLOW
1 set of registers
IMA
OVERFLOW
4 registers
Note *: These 2 IRQ signals are
only present in IRQ Status
register for Link 0.
Figure 18 - IRQ Register Hierarchy
34
MITEL [ MITEL NETWORKS CORPORATION ]
