VDP 313xY
ADVANCE INFORMATION
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
Picture Frame Generator
47
11
9
w v
bit[7:0]
bit[8]
reserved, set t o zero
enable picture frame generator
0
1
PFGEN
picture frame color 12 bit wide,
PFC
16
w h
bit[3:0]
bit[7:4]
0..15
0..15
blue amplitude
green amplitude
red amplitude
0
0
0
PFCB
PFCG
PFCR
bit[11:8] 0..15
picture frame insertion contrast for R
(ampl. range: 0 to 255)
PFRCT
PFGCT
PFBCT
PFGHB
4C
48
9
9
w v
bit[3:0]
bit[7:4]
reserved, set to zero
8
0..13
R amplitude =
PFCR × (PFRCT + 4)
invalid
14,15
picture frame insertion contrast for G
(ampl. range: 0 to 255)
w v
bit[3:0]
bit[7:4]
reserved, set to zero
8
0..13
G amplitude =
PFCG × (PFGCT + 4)
invalid
14,15
picture frame insertion contrast for B
(ampl. range: 0 to 255)
44
4F
9
9
w v
w v
bit[3:0]
bit[7:4]
reserved, set to zero
8
0
0..13
B amplitude =
PFCB × (PFBCT + 4)
14,15
invalid
bit[8:0]
horizontal picture frame begin
code 0 = picture frame generator horizontally disabled
code 1FF = full frame
53
63
9
9
w v
w v
bit[8:0]
bit[8:0]
horizontal picture frame end
vertical picture frame begin
0
PFGHE
PFGVB
270
code 0 = picture frame generator vertically disabled
6F
9
w v
bit[8:0]
vertical picture frame end
56
PFGVE
Priority Decoder
75
9
w v
w v
bit[7]
bit[7]
0/1
0/1
select main/side setting for
contrast,brightness,matrix
0
0
SIDE
79
9
disable/enable peaking transient
suppression when signal is
switched to the picture frame
PKTRNS
34
Micronas
MICRONAS [ MICRONAS ]
