ADVANCE INFORMATION
VDP 313xY
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
Chrominance Channel
14
5E
8
w/r
luma/chroma matching delay
LCM
bit[2:0]
bit[7:3]
−3...3
variable chroma delay
0
CDEL
reserved, set to 0
9
w v
digital transient improvement
DTI
bit[3:0]
bit[7:4]
bit[8]
0..15
0..15
0/1
coring value
1
5
1
DTICO
DTIGA
DTIMO
DTI gain
narrow/wide bandwidth mode
Inverse Matrix
main matrix coefficient R−Y = MR1M×CB+MR2M×CR
7C
74
9
w v
w v
bit[8:0]
bit[8:0]
−256/128 ... 255/128
−256/128 ... 255/128
0
MR1M,
MR2M
9
86
main matrix coefficient G−Y = MG1M×CB+MG2M×CR
6C
64
9
9
w v
w v
bit[8:0]
bit[8:0]
−256/128 ... 255/128
−256/128 ... 255/128
−22
−44
MG1M,
MG2M
main matrix coefficient B−Y = MB1M×CB + MB2M×CR
5C
54
9
9
w v
w v
bit[8:0]
bit[8:0]
−256/128 ... 255/128
−256/128 ... 255/128
113
0
MB1M,
MB2M
side matrix coefficient R−Y = MR1S×CB + MR2S×CR
78
70
9
9
w v
w v
bit[8:0]
bit[8:0]
−256/128 ... 255/128
−256/128 ... 255/128
0
MR1S,
MR2S
73
side matrix coefficient G−Y = MG1S×CB + MG2S×CR
68
60
9
9
w v
w v
bit[8:0]
bit[8:0]
−256/128 ... 255/128
−256/128 ... 255/128
−19
−37
MG1S,
MG2S
side matrix coefficient B−Y = MB1S×CB + MB2S×CR
58
50
9
9
w v
w v
bit[8:0]
bit[8:0]
−256/128 ... 255/128
−256/128 ... 255/128
97
0
MB1S,
MB2S
Micronas
33
MICRONAS [ MICRONAS ]
