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MAS3507D 参数 Datasheet PDF下载

MAS3507D图片预览
型号: MAS3507D
PDF下载: 下载PDF文件 查看货源
内容描述: MPEG 1/2 2/3层音频解码器 [MPEG 1/2 Layer 2/3 Audio Decoder]
分类和应用: 解码器
文件页数/大小: 60 页 / 816 K
品牌: MICRONAS [ MICRONAS ]
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PRELIMINARY DATA SHEET  
MAS 3507D  
2.8. Start-up Configuration  
Table 2–8: Start-up configuration1)  
Basic operation of the MAS 3507D is possible without  
controller interaction. Configuration and the most  
important status information are available by the PIO  
interface. The start-up configuration is selected  
according to the levels of several PIO pins. The levels  
should be set via high impedance resistors (for exam-  
ple 10 kΩ) to VSS or VDD and will be copied into the  
StartupConfig register directly after power up / reset.  
After start-up, the PIO will be reconfigured as output.  
PIO  
Pin  
“0”  
“1”  
PI8  
divide CLKO by 1,  
2, or 4 (according  
to MPEG 1, 2, or  
2.5)  
CLKO fixed at  
24.576 or  
22.5792 MHz  
PI4  
SDI input mode  
PIO-DMA input  
mode  
To enable greater flexibility, it is possible to configure  
the MAS 3507D without using the PIO pins or to recon-  
figure the IC after start-up. The procedure for this is to  
send two I2C commands to the MAS 3507D:  
PI3  
PI2  
PI1  
PI0  
Enable layer 3  
Disable layer 3  
Disable layer 2  
SDO output: 16 bit  
Enable layer 2  
– Writing the StartupConfig register (see Section 3.6.  
on page 26)  
SDO output: 32 bit  
– Execute a ‘run $0fcd’ command (see  
Section 3.3.1.).  
input: Multimedia  
mode (PLL off)  
input: Broadcast  
mode (PLL on)  
The configuration will be active up to a reset. Then, the  
new configuration will be loaded again via PIO.  
1) Start-up setting can be changed by I2C commands  
after reset.  
2.8.1. Parallel Input Output Interface (PIO)  
During start-up, the PIO will read the start-up configu-  
ration. This is to define the environment for the  
MAS 3507D. The following pins must be connected via  
resistors to VSS or VDD:  
Micronas  
15  
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