MAS 3507D
PRELIMINARY DATA SHEET
2.7.4.2. Mode 2:32 Bit/Sample (Inverted SOI)
2.7.4.3. Other Output Modes
If the serial output generates 32 bits per audio sample,
only the first 20 bits will carry valid audio data. The 12
trailing bits are set to zero by default (see Fig. 2–7)
The interface is also configurable by software to work
in different modes. It is possible to choose:
– 16 or 32 bit/sample modes,
The 12 trailing bits for left and right channel of the SDO
interface can be accessed by writing to registers as
shown in Table 2–7.
– inverted or noninverted word strobe (SOI),
– no delay or delay of data related to word strobe
– inverted or noninverted I2S-Clock (SOC).
Table 2–7: Access for Trailing Bits
For further details see Section 3.7.2.2.
Register
$c5
Bit 0 ... 11
Left Channel
Right Channel
$c6
V
V
h
...
...
SOC
l
V
V
h
SOD
SOI
...
31
30 29 28 27 26 25 ... 7
0
6 5 4 3 2 1 0
31 30 29 28 27 26 25
7
6
5
4
3
2
1
l
V
V
h
l
right 32-bit audio sample
left 32-bit audio sample
Fig. 2–7: Schematic timing of the SDO interface in 32 bit/sample mode
14
Micronas
MICRONAS [ MICRONAS ]
