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MAS3507D 参数 Datasheet PDF下载

MAS3507D图片预览
型号: MAS3507D
PDF下载: 下载PDF文件 查看货源
内容描述: MPEG 1/2 2/3层音频解码器 [MPEG 1/2 Layer 2/3 Audio Decoder]
分类和应用: 解码器
文件页数/大小: 60 页 / 816 K
品牌: MICRONAS [ MICRONAS ]
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MAS 3507D  
PRELIMINARY DATA SHEET  
2.9. Status Pins in SDI Input Mode  
Table 2–9: PIO output signals during MPEG decoding  
in SDI mode  
After having read the start-up configuration, the PIO  
will be switched to ‘µP-mode’. In µP-mode, the addi-  
tional PIO control lines (PR, PCS) are evaluated. If the  
MPEG decoder firmware detects PR = ‘1’ and the  
PCS = ‘0’. Then, all PIO interface lines are configured  
as output and display some status information of the  
MPEG decoder. The PIO lines can be read by an  
external controller or directly used by dedicated hard-  
ware blocks (e.g. for sample rate indication or display  
units). The internal MPEG decoder firmware attaches  
specific functions to the following pins.  
PIO  
Pin  
Name  
Comment  
PI19  
Demand PIN  
%0  
%1  
no input data exp.  
input data request  
PI18, MPEG INDEX  
PI17  
%00  
MPEG 2.5  
reserved  
MPEG 2  
MPEG 1  
%01  
%10  
%11  
The MPEG-FRAME-SYNC signal is set to ‘1’ after the  
internal decoding for the MPEG header has been fin-  
ished for one frame. The rising edge of this signal  
could be used as an interrupt input for the controller  
that triggers the read out of the control information and  
ancillary data. As soon as the MAS 3507D has recog-  
nized the corresponding read command (‘read control  
interface data’ (see Section 3.3.2. on page 21), the  
MPEG-FRAME-SYNC is reset. This behavior reduces  
the possibility of missing the MPEG-FRAME-SYNC  
active state.  
PI13, MPEG Layer ID  
PI12  
%00  
reserved  
Layer 3  
%01  
%10  
%11  
Layer 2  
Layer 11)  
PI8  
PI4  
MPEG CRC-ERROR  
%0  
%1  
no error  
CRC-error,  
MPEG decoding  
not successful  
tframe=24 ... 72 ms  
tread  
MPEG-FRAME-  
SYNC  
V
l
h
see following text  
in kHz2)  
PI3,  
PI2  
Sampling frequency  
MPEG-FRAME-SYNC  
%00  
%01  
%10  
%11  
44.1 / 22.1 / 11.0  
48 / 24 / 12  
32 / 16 / 8  
Fig. 2–8: Schematic timing of MPEG-FRAME-Sync  
reserved  
The time tread depends on the response time of the  
controller. This time must not exceed 1/2 of the MPEG-  
frame length tframe. The MPEG frame lengths are given  
in Table 2–10  
PI1,  
PI0  
Deemphasis  
%00  
%01  
%10  
%11  
none  
50/15 µs  
reserved  
CCITT J.17  
1)  
Layer 1 bit streams will not be decoded  
Sampling frequency also defined by MPEG index  
(see Table 3–12 for additional information)  
2)  
.
16  
Micronas  
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