CIP 3250A
ADVANCE INFORMATION
3.6.3.11. Characteristics Picture Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
V
OL
Output Low Voltage
RC[7...0],
GL[7..0],
B[7..0]
–
–
0.4
V
Load as described at
I C:<14>LOAD
2
V
OH
Output High Voltage
(only in Push-pull Mode)
2.4
–
–
V
Load as described at
2
I C:<14>LOAD
2
I C:<14>PUDIS = 0
t
t
t
Output Delay Time after
active Clock Transition
–
6
6
–
–
–
35
–
ns
ns
ns
Load as described at
I C:<14>LOAD
OD
2
Output Hold Time after
active Clock Transition
OH
Output Low Hold Time after
active Clock Transition
15
OHL
CLK Input
see NOTE
t
OD
PICTURE
Output
Push-pull Mode
V
OH
Data valid
V
OL
t
t
OHP
t
t
OHL
OD
PICTURE
Output
Open Drain Mode
V
PUP
Data valid
V
OL
OH
2
Fig. 3–20: Picture output
Note: active clock edge depends on I C:<17>NEGCLK
Micronas
41
MICRONAS [ MICRONAS ]
