CIP 3250A
ADVANCE INFORMATION
3.6.3.4. Characteristics Main Clock Input
Symbol
Parameter
Pin Name
Min.
1.5
Typ.
Max.
3.5
Unit
V
Test Conditions
V
V
ΦM Main Clock Input DC Voltage
CLK
–
–
Φ
MIDC
MIAC
ΦM Main Clock Input
AC Voltage (p–p)
0.8
2.5
V
Φ
t
t
ΦM Clock Input
High to Low Ratio
2
3
1
1
3
2
Φ
MIH
Φ
MIL
t
ΦM Clock Input
High to Low Transition Time
–
–
–
–
0.15
f
Φ
M
Φ
MIHL
t
Φ
ΦM Clock Input
0.15
MILH
Low to High Transition Time
f
Φ
M
t
t
Φ
t
Φ
t
Φ
MIL
Φ
MILH
MIAC
MIHL
MIH
CLK Input
V
Φ
MIDC
V
Φ
0 V
Fig. 3–14: Main clock input
3.6.3.5. Characteristics Active Video Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
V
OL
Output Low Voltage
AVO
–
–
0.4
V
Load as described at
I C:<14>LOAD
2
V
Output High Voltage
2.4
–
–
–
–
–
V
Load as described at
I C:<14>LOAD
OH
2
t
t
Output Delay TIme after
active Clock Transition
35
–
ns
ns
Load as described at
OD
2
I C:<14>LOAD
Output Hold Time after
active Clock Transition
6
OH
CLK Input
see NOTE
t
t
t
t
OD
OD
OH
OH
V
OH
AVO Output
V
OL
2
Fig. 3–15: Active video output
Note: active clock edge depends on I C:<17>NEGCLK
Micronas
37
MICRONAS [ MICRONAS ]
