CIP 3250A
ADVANCE INFORMATION
3.6.3.10. Characteristics Priority Input/Output
Symbol
Parameter
Pin Name
Min.
–
Typ.
Max.
0.8
–
Unit
V
Test Conditions
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
PRIO[2...0]
–
–
–
IL
1.5
–
V
IH
OL
0.6
V
Load as described at
2
I C:<14>LOAD
I
Pullup Current
Pullup Voltage
1.2
1.8
7
–
2.0
2.5
–
mA
V
@ 1 Volt
PUP
V
2.0
–
PUP
t
t
t
t
t
Input Setup Time before
active Clock Transition
ns
IS
Input Hold Time after
active Clock Transition
5
–
6
6
–
–
–
–
–
ns
ns
ns
ns
IH
Output Delay Time after
active Clock Transition
35
–
Load as described at
OD
OH
OHL
2
I C:<14>LOAD
Output Hold Time after
active Clock Transition
Output Low Hold Time after
active Clock Transition
15
CLK Input
see NOTE
t
IS
t
IH
V
IH
PRIO Input
Data valid
V
IL
t
t
OHL
OD
V
PUP
PRIO Output
Data valid
V
OL
t
OH
2
Fig. 3–19: Priority input/output
Note: active clock edge depends on I C:<17>NEGCLK
40
Micronas
MICRONAS [ MICRONAS ]
