CIP 3250A
ADVANCE INFORMATION
3.6.3.6. Characteristics Active Video Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
2
V
IL
Input Low Voltage
AVI
–
–
–
–
1.3
0.8
V
V
I C:<17>D2KSYNC = 1
2
I C:<17>D2KSYNC = 0
2
V
IH
Input High Voltage
3.3
1.5
–
–
–
–
V
V
I C:<17>D2KSYNC = 1
2
I C:<17>D2KSYNC = 0
t
t
Input Setup Time before
active Clock Transition
7
5
–
–
–
–
ns
ns
IS
Input Hold Time after
active Clock Transition
IH
CLK Input
see NOTE
t
IS
t
IH
V
IH
AVI Input
Data valid
V
IL
2
Fig. 3–16: Active video input
Note: active clock edge depends on I C:<17>NEGCLK
3.6.3.7. Characteristics Fsync Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
2
V
IL
Input Low Voltage
FSY
–
–
–
–
1.3
0.8
V
V
I C: D2KSYNC = 1
2
I C: D2KSYNC = 0
2
V
IH
Input High Voltage
3.3
1.5
–
–
–
–
V
V
I C: D2KSYNC = 1
2
I C: D2KSYNC = 0
t
t
Input Setup TIme before
active Clock Transition
7
5
–
–
–
–
ns
ns
IS
Input Hold Time after active
active Clock Transition
IH
CLK Input
see NOTE
t
IS
t
IH
V
IH
FSY Input
Data valid
V
IL
2
Fig. 3–17: Fsync input
Note: active clock edge depends on I C:<17>NEGCLK
38
Micronas
MICRONAS [ MICRONAS ]
