CIP 3250A
ADVANCE INFORMATION
2
3.6.3.8. Characteristics I C Bus Interface Input/Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
V
Test Conditions
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
SDA,
SCL
–
–
–
–
0.3*V
IL
DD
0.6*V
–
V
IH
OL
DD
–
0.4
0.6
V
V
I = 3 mA
I
I = 6 mA
I
t
f
t
t
t
t
t
Signal Fall Time
Clock Frequency
–
–
–
–
–
–
–
–
300
400
–
ns
kHz
ns
ns
ns
ns
ns
C = 400 pF
L
F
SCL
0
SCL
I2C3
I2C4
I2C1
I2C2
I2C5
2
I C-Clock Low Pulse Time
500
500
120
120
55
2
I C-Clock High Pulse Time
–
2
I C Start Condition Setup Time
SCL,
SDA
–
2
I C Stop Condition Setup Time
–
2
I C-Data Setup Time Before
–
Rising Edge of Clock SCL
2
t
t
I C-Data Hold Time after
55
50
–
–
–
–
ns
I2C6
Falling Edge of Clock SCL
2
I C-Slew Times at
V/µs
I2C7
2
I C-Clock = 1 MHz
3.6.3.9. Characteristics Luma/Chroma Input
Symbol
Parameter
Pin Name
Min.
–
Typ.
Max.
0.8
–
Unit
V
Test Conditions
V
V
Input Low Voltage
Input High Voltage
Pullup Current
L[7..0],
C[7..0]
–
–
IL
1.5
V
IH
2
@ 1 Volt / I C:<06>D2KIN = 1
I
1.5
–
2.1
–
3.0
±1
mA
µ A
PUP
2
@ 1 Volt / I C:<06>D2KIN = 0
2
V
PUP
Pullup Voltage
1.8
–
–
–
3.2
–
V
V
I C:<06>D2KIN = 1
2
I C:<06>D2KIN = 0
t
t
Input Setup Time before
active Clock Transition
7
5
–
–
–
–
ns
ns
IS
Input Hold Time after
actice Clock Transition
IH
CLK Input
see NOTE
t
IS
t
IH
V
IH
L/C Input
Data valid
V
IL
2
Fig. 3–18: Luma/chroma input
Note: active clock edge depends on I C:<17>NEGCLK
Micronas
39
MICRONAS [ MICRONAS ]
