512Mb, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Table 17: Flag Status Register Bit Definitions (Continued)
Note 1 applies to entire table
Bit Name Settings
Description
Notes
0
Addressing
0 = 3 bytes addressing
1 = 4 bytes addressing
Status bit: Indicates whether 3-byte or 4-byte address
mode is enabled.
2
1. Register bits are read by READ FLAG STATUS REGISTER command. All bits are volatile.
2. Status bits are reset automatically.
Notes:
3. Error bits must be cleared through the CLEAR FLAG STATUS REGISTER command.
4. These error flags are "sticky." They must be cleared through the CLEAR STATUS REGIS-
TER command.
5. Program or erase controller bit = NOT (write in progress bit).
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n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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