512Mb, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Table 12: Sequence of Bytes During Wrap
Starting Address
16-Byte Wrap
32-Byte Wrap
64-Byte Wrap
0
0-1-2- . . . -15-0-1- . .
0-1-2- . . . -31-0-1- . .
0-1-2- . . . -63-0-1- . .
1-2- . . . -63-0-1-2- . .
15-16-17- . . . -63-0-1- . .
31-32-33- . . . -63-0-1- . .
63-0-1- . . . -63-0-1- . .
1
1-2- . . . -15-0-1-2- . .
1-2- . . . -31-0-1-2- . .
15
31
63
15-0-1-2-3- . . . -15-0-1- . .
31-16-17- . . . -31-16-17- . .
63-48-49- . . . -63-48-49- . .
15-16-17- . . . -31-0-1- . .
31-0-1-2-3- . . . -31-0-1- . .
63-32-33- . . . -63-32-33- . .
Table 13: Supported Clock Frequencies – STR
Note 1 applies to entire table
Number of Dummy
Clock Cycles
DUAL OUTPUT
FAST READ
DUAL I/O FAST
READ
QUAD OUTPUT QUAD I/O FAST
FAST READ
90
FAST READ
READ
1
2
80
50
70
43
60
30
100
90
40
3
108
100
80
75
50
4
108
105
90
90
60
5
108
108
100
105
108
108
108
108
100
105
108
108
108
108
70
6
108
108
80
7
108
108
86
8
108
108
95
9
108
108
105
108
10
108
108
1. Values are guaranteed by characterization and not 100% tested in production.
Note:
Table 14: Supported Clock Frequencies – DTR
Note 1 applies to entire table
Number of Dummy
Clock Cycles
DUAL OUTPUT
FAST READ
DUAL I/O FAST
READ
QUAD OUTPUT QUAD I/O FAST
FAST READ
FAST READ
READ
1
2
45
50
54
54
54
54
54
54
54
54
40
45
50
53
54
54
54
54
54
54
25
35
40
45
50
53
54
54
54
54
30
38
45
47
50
53
54
54
54
54
15
20
3
25
4
30
5
35
6
40
7
43
8
48
9
53
10
54
1. Values are guaranteed by characterization and not 100% tested in production.
Note:
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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