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N25Q512A13GF840E 参数 Datasheet PDF下载

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型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Nonvolatile and Volatile Registers  
Table 15: Extended Address Register Bit Definitions  
Note 1 applies to entire table  
Bit Name  
Settings  
Description  
7
6
5
4
3
2
1
0
A[31:26]  
0 = Reserved  
A[25:24]  
11 = Upper 128Mb segment  
10 = Third 128Mb segment  
01 = Second 128Mb segment  
Enable selecting 128Mb segmentation. For A[25:24] ,  
the default setting is determined by bit 1 of the non-  
volatile configuration register. However, this setting  
00 = Lower 128Mb segment (default)  
can be changed using the WRITE EXTENDED AD-  
DRESS REGISTER command.  
1. The extended address register is for an application that supports only 3-byte addressing.  
It extends the device's first three address bytes A[23:0] to a fourth address byte A[31:24]  
to enable memory access beyond 128Mb. The extended address register bits [1:0] are  
used to select one of the four 128Mb segments of the memory array. If 4-byte address-  
ing is enabled, extended address register settings are ignored.  
Note:  
Enhanced Volatile Configuration Register  
Table 16: Enhanced Volatile Configuration Register Bit Definitions  
Note 1 applies to entire table  
Bit  
Name  
Settings  
Description  
Notes  
7
Quad I/O protocol  
0 = Enabled  
Enables or disables quad I/O protocol.  
2
1 = Disabled (Default,  
extended SPI protocol)  
6
Dual I/O protocol  
0 = Enabled  
Enables or disables dual I/O protocol.  
2
1 = Disabled (Default,  
extended SPI protocol)  
5
4
Reserved  
x = Default  
0b = Fixed value.  
Reset/hold  
0 = Disabled  
Enables or disables hold or reset.  
1 = Enabled (Default)  
(Available on dedicated part numbers.)  
3
VPP accelerator  
0 = Enabled  
Enables or disables VPP acceleration for QUAD  
1 = Disabled (Default) INPUT FAST PROGRAM and QUAD INPUT EX-  
TENDED FAST PROGRAM OPERATIONS.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
24  
© 2011 Micron Technology, Inc. All rights reserved.  
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