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N25Q512A13GF840E 参数 Datasheet PDF下载

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型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Nonvolatile and Volatile Registers  
Status Register  
Table 9: Status Register Bit Definitions  
Note 1 applies to entire table  
Bit  
Name  
Settings  
Description  
Notes  
7
Status register  
0 = Enabled  
Nonvolatile bit: Used with the W# signal to enable or dis-  
3
write enable/disable 1 = Disabled  
able writing to the status register.  
5
Top/bottom  
0 = Top  
1 = Bottom  
Nonvolatile bit: Determines whether the protected mem-  
ory area defined by the block protect bits starts from the  
top or bottom of the memory array.  
4
4
6, 4:2 Block protect 3–0  
See Protected Area Nonvolatile bit: Defines memory to be software protec-  
Sizes – Upper Area ted against PROGRAM or ERASE operations. When one or  
and Lower Area ta- more block protect bits is set to 1, a designated memory  
bles in Device Pro-  
tection  
area is protected from PROGRAM and ERASE operations.  
1
0
Write enable latch  
Write in progress  
0 = Cleared (Default) Volatile bit: The device always powers up with this bit  
2, 5  
2, 6  
1 = Set  
cleared to prevent inadvertent WRITE STATUS REGISTER,  
PROGRAM, or ERASE operations. To enable these opera-  
tions, the WRITE ENABLE operation must be executed first  
to set this bit.  
0 = Ready  
1 = Busy  
Volatile bit: Indicates if one of the following command cy-  
cles is in progress:  
WRITE STATUS REGISTER  
WRITE NONVOLATILE CONFIGURATION REGISTER  
PROGRAM  
ERASE  
1. Bits can be read from or written to using READ STATUS REGISTER or WRITE STATUS REG-  
ISTER commands, respectively.  
Notes:  
2. Volatile bits are cleared to 0 by a power cycle or reset.  
3. The status register write enable/disable bit, combined with the W#/VPP signal as descri-  
bed in the Signal Descriptions, provides hardware data protection for the device as fol-  
lows: When the enable/disable bit is set to 1, and the W#/VPP signal is driven LOW, the  
status register nonvolatile bits become read-only and the WRITE STATUS REGISTER oper-  
ation will not execute. The only way to exit this hardware-protected mode is to drive  
W#/VPP HIGH.  
4. See Protected Area Sizes tables. The DIE ERASE command is executed only if all bits are  
0.  
5. In case of protection error this volatile bit is set and can be reset only by means of a  
CLEAR FLAG STATUS REGISTER command.  
6. Program or erase controller bit = NOT (write in progress bit).  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
19  
© 2011 Micron Technology, Inc. All rights reserved.  
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