欢迎访问ic37.com |
会员登录 免费注册
发布采购

N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号N25Q512A13GF840E的Datasheet PDF文件第17页浏览型号N25Q512A13GF840E的Datasheet PDF文件第18页浏览型号N25Q512A13GF840E的Datasheet PDF文件第19页浏览型号N25Q512A13GF840E的Datasheet PDF文件第20页浏览型号N25Q512A13GF840E的Datasheet PDF文件第22页浏览型号N25Q512A13GF840E的Datasheet PDF文件第23页浏览型号N25Q512A13GF840E的Datasheet PDF文件第24页浏览型号N25Q512A13GF840E的Datasheet PDF文件第25页  
512Mb, Multiple I/O Serial Flash Memory  
Nonvolatile and Volatile Registers  
2. The 0000 and 1111 settings are identical in that they both define the default state,  
which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility.  
3. If the number of dummy clock cycles is insufficient for the operating frequency, the  
memory reads wrong data. The number of cycles must be set according to and sufficient  
for the clock frequency, which varies by the type of FAST READ command, as shown in  
the Supported Clock Frequencies table.  
4. If bits 2 and 3 are both set to 0, the device operates in quad I/O. When bits 2 or 3 are  
reset to 0, the device operates in dual I/O or quad I/O respectively, after the next power-  
on.  
Table 11: Volatile Configuration Register Bit Definitions  
Note 1 applies to entire table  
Bit  
Name  
Settings  
Description  
Notes  
7:4  
Number of dum- 0000 (identical to 1111)  
Sets the number of dummy clock cycles subsequent to  
all FAST READ commands.  
The default setting targets maximum allowed frequen-  
cy and guarantees backward compatibility.  
2, 3  
my clock cycles  
0001  
0010  
.
.
1101  
1110  
1111  
3
XIP  
0
1
Enables or disables XIP. For device part numbers with  
feature digit equal to 2 or 4, this bit is always "Don’t  
Care," so the device operates in XIP mode without set-  
ting this bit.  
2
Reserved  
Wrap  
x = Default  
0b = Fixed value.  
1:0  
00 = 16-byte boundary  
aligned  
16-byte wrap: Output data wraps within an aligned 16-  
byte boundary starting from the address (3-byte or 4-  
byte) issued after the command code.  
4
01 = 32-byte boundary  
aligned  
32-byte wrap: Output data wraps within an aligned 32-  
byte boundary starting from the address (3-byte or 4-  
byte) issued after the command code.  
10 = 64-byte boundary  
aligned  
64-byte wrap: Output data wraps within an aligned 64-  
byte boundary starting from the address (3-byte or 4-  
byte) issued after the command code.  
11 = sequential (default)  
Continuous reading (default): All bytes are read se-  
quentially.  
1. Settings determine the device memory configuration upon a change of those settings by  
the WRITE VOLATILE CONFIGURATION REGISTER command. The register is read from or  
written to by READ VOLATILE CONFIGURATION REGISTER or WRITE VOLATILE CONFIGU-  
RATION REGISTER commands respectively.  
Notes:  
2. The 0000 and 1111 settings are identical in that they both define the default state,  
which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility.  
3. If the number of dummy clock cycles is insufficient for the operating frequency, the  
memory reads wrong data. The number of cycles must be set according to and be suffi-  
cient for the clock frequency, which varies by the type of FAST READ command, as  
shown in the Supported Clock Frequencies table.  
4. See the Sequence of Bytes During Wrap table.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
21  
© 2011 Micron Technology, Inc. All rights reserved.  
 复制成功!