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N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
SPI Protocols  
SPI Protocols  
Table 8: Extended, Dual, and Quad SPI Protocols  
Com-  
Protocol  
Name  
mand  
Input  
Address  
Input  
Data  
Input/Output Description  
Multiple DQn Device default protocol from the factory. Additional com-  
Extended  
Dual  
DQ0  
Multiple DQn  
lines, depending lines, depending mands extend the standard SPI protocol and enable address  
on the command on the command or data transmission on multiple DQn lines.  
DQ[1:0]  
DQ[1:0]  
DQ[1:0]  
Volatile selectable: When the enhanced volatile configu-  
ration register bit 6 is set to 0 and bit 7 is set to 1, the de-  
vice enters the dual SPI protocol immediately after the  
WRITE ENHANCED VOLATILE CONFIGURATION REGISTER  
command. The device returns to the default protocol after  
the next power-on. In addition, the device can return to de-  
fault protocol using the rescue sequence or through new  
WRITE ENHANCED VOLATILE CONFIGURATION REGISTER  
command, without power-off or power-on.  
Nonvolatile selectable: When nonvolatile configuration  
register bit 2 is set, the device enters the dual SPI protocol  
after the next power-on. Once this register bit is set, the de-  
vice defaults to the dual SPI protocol after all subsequent  
power-on sequences until the nonvolatile configuration  
register bit is reset to 1.  
Quad1  
DQ[3:0]  
DQ[3:0]  
DQ[3:0]  
Volatile selectable: When the enhanced volatile configu-  
ration register bit 7 is set to 0, the device enters the quad  
SPI protocol immediately after the WRITE ENHANCED VOL-  
ATILE CONFIGURATION REGISTER command. The device re-  
turns to the default protocol after the next power-on. In ad-  
dition, the device can return to default protocol using the  
rescue sequence or through new WRITE ENHANCED VOLA-  
TILE CONFIGURATION REGISTER command, without power-  
off or power-on.  
Nonvolatile selectable: When nonvolatile configuration  
register bit 3 is set to 0, the device enters the quad SPI pro-  
tocol after the next power-on. Once this register bit is set,  
the device defaults to the quad SPI protocol after all subse-  
quent power-on sequences until the nonvolatile configura-  
tion register bit is reset to 1.  
1. In quad SPI protocol, all command/address input and data I/O are transmitted on four  
lines except during a PROGRAM and ERASE cycle performed with VPP. In this case, the  
device enters the extended SPI protocol to temporarily allow the application to perform  
a PROGRAM/ERASE SUSPEND operation or to check the write-in-progress bit in the sta-  
tus register or the program/erase controller bit in the flag status register. Then, when  
VPP goes LOW, the device returns to the quad SPI protocol.  
Note:  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
17  
© 2011 Micron Technology, Inc. All rights reserved.  
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