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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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N25Q128 - 1.8 V  
Description  
The memory can be write protected by software using a mix of volatile and non-volatile  
protection features, depending on the application needs. The protection granularity is of 64-  
Kbyte (sector granularity) for volatile protections.  
The N25Q128 has 64 one-time-programmable bytes (OTP bytes) that can be read and  
programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP  
(POTP), respectively. These 64 bytes can be permanently locked by a particular Program  
OTP (POTP) sequence. Once they have been locked, they become read-only and this state  
cannot be reversed.  
Many different N25Q128 configurations are available, please refer to the ordering scheme  
page for the possibilities. Additional features are available as security options (The Security  
features are described in a dedicated Application Note). Please contact your nearest  
Numonyx Sales office for more information.  
Figure 1.  
Logic diagram  
V
CC  
DQ0  
C
DQ1  
S
W/V /DQ2  
PP  
HOLD/DQ3  
V
SS  
Logic_Diagram_x25x  
Note:  
Reset functionality is available in devices with a dedicated part number. See Section 16:  
Ordering information.  
Table 1.  
Signal names  
Signal  
Description  
I/O  
C
Serial Clock  
Input  
I/O(1)  
I/O(2)  
Input  
I/O(3)  
I/O(3)  
DQ0  
Serial Data input  
Serial Data output  
Chip Select  
DQ1  
S
W/VPP/DQ2  
HOLD/DQ3(4)  
VCC  
Write Protect/Enhanced Program supply voltage/additional data I/O  
Hold (Reset function available upon customer request)/additional data I/O  
Supply voltage  
Ground  
VSS  
1. Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and quad  
I/O for Quad I/O SPI protocol instructions.  
2. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and  
quad instruction input for Quad I/O SPI protocol.  
3. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.  
4. Reset functionality available with a dedicated part number. See Section 16: Ordering information.  
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