Description
N25Q128 - 1.8 V
1
Description
The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection
mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility
to work in XIP (“eXecute in Place”) mode.
The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new
instructions allow to double or quadruple the transfer bandwidth for read and program
operations.
Furthermore the memory can be operated with 3 different protocols:
Standard SPI (Extended SPI protocol)
Dual I/O SPI
Quad I/O SPI
The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI
protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data
are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions
codes, the addresses and the data are always transmitted across four data lines thus
enabling a tremendous improvement in both random access time and data throughput.
The memory can work in “XIP mode”, that means the device only requires the addresses
and not the instructions to output the data. This mode dramatically reduces random access
time thus enabling many applications requiring fast code execution without shadowing the
memory content on a RAM.
The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be
entered and exited using different dedicated instructions to allow maximum flexibility: for
applications required to enter in XIP mode right after power up of the device, this can be set
as default mode by using dedicated Non Volatile Register (NVR) bits.
It is also possible to reduce the power on sequence time with the Fast POR (Power on
Reset) feature, enabling a reduction of the latency time before the first read instruction can
be performed. Another feature is the ability to pause and resume program and erase cycles
by using dedicated Program/Erase Suspend and Resume instructions.
The N25Q128 memory offers the following additional Features to be configured by using the
Non Volatile Configuration Register (NVCR) for default /Non-Volatile settings or by using the
Volatile and Volatile Enhanced Configuration Registers for Volatile settings:
the number of dummy cycles for fast read instructions (single, dual and, quad I/O)
according to the operating frequency
the output buffer impedance
the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI)
the required XIP mode
Fast or standard POR sequence
the Hold (Reset) functionality enabling/disabling
The memory is organized as 248 (64-Kbyte) main sectors, in products with Bottom or Top
architecture there are 8 64-Kbyte boot sectors, and each boot sector is further divided into
16 4-Kbyte subsectors (128 subsectors in total). The boot sectors can be erased a 4-Kbyte
subsector at a time or as a 64-Kbyte sector at a time. The entire memory can be also erased
at a time or by sector.
12/185
MICRON [ MICRON TECHNOLOGY ]
