N25Q128 - 1.8 V
Signal descriptions
2.5
Hold (HOLD) or Reset (Reset)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
Reset functionality is present instead of Hold in devices with a dedicated part number. See
Section 16: Ordering information.
During Hold condition, the Serial Data output (DQ1) is in high impedance, and Serial Data
input (DQ0) and Serial Clock (C) are Don't Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
For devices featuring Reset instead of Hold functionality, the Reset (Reset) input provides a
hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast
Program (QIEFP) instructions, the Hold (Reset) / DQ3 is used as an input/output (DQ3
functionality).
In QIO-SPI, the Hold (Reset) / DQ3 pin acts as an I/O (DQ3 functionality), and the HOLD
(Reset) functionality disabled when the device is selected. When the device is deselected (S
signal is high), in parts with Reset functionality, it is possible to reset the device unless this
functionality is not disabled by mean of dedicated registers bits.
The HOLD (Reset) functionality can be disabled using bit 3 of the NVCR or bit 4 of the VECR.
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