N25Q128 - 1.8 V
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Extended SPI protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 33
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Read identification instruction and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 11. Read Data Bytes instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence . . . . . . . . . . . . . . . 82
Figure 13. Dual Output Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 14. Dual I/O Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 15. Quad Input/Output Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 16. Quad Input/ Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 17. Read OTP instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 18. Write Enable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 19. Write Disable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 20. Page Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 21. Dual Input Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 22. Dual Input Extended Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 23. Quad Input Fast Program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 24. Quad Input Extended Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 25. Program OTP instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 26. How to permanently lock the OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 27. Subsector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 28. Sector Erase instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 29. Bulk Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 30. Read Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 31. Write Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 32. Read Lock Register instruction and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 33. Write to Lock Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 34. Read Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 35. Clear Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 36. Read NV Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 37. Write NV Configuration Register instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 38. Read Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 39. Write Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 40. Read Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 110
Figure 41. Write Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 111
Figure 42. Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 43. Release from Deep Power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 44. Multiple I/O Read Identification instruction and data-out sequence DIO-SPI . . . . . . . . . . 115
Figure 45. Dual Command Fast Read instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . 116
Figure 46. Read OTP instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 47. Write Enable instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 48. Write Disable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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MICRON [ MICRON TECHNOLOGY ]
