‡
Pre lim in a ry
MT9V012 - 1/6-In ch VGA CMOS Dig it a l Im a g e Se n so r
Ele ct rica l Sp e cifica t io n s
Fig u re 32: Ackn o w le d g e Sig n a l Tim in g Aft e r a n 8-Bit Writ e t o t h e Se n so r
6
3
SCLK
Sensor pulls down
DATA pin
S
SDATA
Fig u re 33: Ackn o w le d g e Sig n a l Tim in g Aft e r a n 8-Bit Re a d fro m t h e Se n so r
7
6
SCLK
Sensor tri-states SDATA pin
(turns off pull down)
SDATA
Note:
After a read, the master receiver must drive SDATA LOW to acknowledge receipt of data
bits. When read sequence is complete, the master must generate a no acknowledge by
leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used.
Fig u re 34: Typ ica l Sp e ct ra l Ch a ra ct e rist ics
Quantum Efficie ncy
40
35
30
25
20
15
10
5
R
G
B
0
350
450
550
650
750
850
950
1050
Wavelength (nm)
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
51
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