‡
Pre lim in a ry
MT9V012 - 1/6-In ch VGA CMOS Dig it a l Im a g e Se n so r
Ele ct rica l Sp e cifica t io n s
Ta b le 14: AC Ele ct rica l Ch a ra ct e rist ics: 2.50V–3.10V
VPWR = 2.50V–3.10V; TA = Ambient = 25°C
Sym b o l
De fin it io n
Co n d it io n
Min
Typ
Ma x
Un it s
fCLKIN
Input Clock Frequency Clock
Duty Cycle
1
27
MHz
MIN/MAX
tR
tF
tPLHP
Input Clock Rise Time
Input Clock Fall Time
TBD
TBD
ns
ns
ns
CLOAD = 10pF
CLOAD = 10pF
CLOAD = 10pF
CLOAD = 10pF
CLKIN to PIXCLK propagation delay
LOW-to-HIGH
tPHLP
tPLHD
tPHLD
CLKIN to PIXCLK propagation delay
HIGH-to-LOW
ns
ns
ns
CLKIN to DOUT(9:0)propagation delay
LOW-to-HIGH
CLKIN to DOUT(9:0) propagation delay
HIGH-to-LOW
tOH
tPLHF,L
Data Hold Time
ns
ns
CLOAD = 10pF
TBD
TBD
CLKIN to FRAME_VALID and LINE_VALID
propagation
LOW-to-HIGH
tPHLF,L
CLKIN to FRAME_VALID and LINE_VALID
propagation
ns
HIGH-to-LOW
tETSU
tETH
VRR_N, ESR_N, HPA_N input setup to rising
edge of CLKIN
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
VRR_N, ESR_N, HPA_N input hold from
rising edge of CLKIN
tPHLF
tPHLF
tOED
CLKIN to flash propagation delay
LOW-to-HIGH
CLKIN to flash propagation delay
HIGH-to-LOW
TBD
TBD
STANDBY LOW to FRAME_VALID,
LINE_VALID, PIXCLK, DOUT(9:0), flash
driven
tOEZ
STANDBY HIGH to FRAME_VALID,
LINE_VALID, PIXCLK, DOUT(9:0), flash
floating
TBD
ns
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
47
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