‡
Pre lim in a ry
MT9V012 - 1/6-In ch VGA CMOS Dig it a l Im a g e Se n so r
Fe a t u re De scrip t io n
2. Set Reg0x22[9] = 1
When Reg0x22[9] = 1, LINE_VALID is asserted 22 pixel clocks earlier than normal. Data
from columns from 21 through 2 (20 columns) is followed by two pixel clocks of unde-
fined data, then by data from the visible columns (controlled by Reg0x02, Reg0x04, and
Reg0x20).
Clo ck Co n t ro l
The MT9V012 uses an aggressive clock-gating methodology to reduce power consump-
tion: the clocked logic is divided into a number of separate domains, each of which is
only clocked as required. Reg0x65 can be used to bypass the clock gating, so that clocks
to individual domains run continuously.
When the MT9V012 enters a low-power state, almost all of the internal clocks are
stopped. The only exception is that a small amount of logic (approximately 10 flip-flops)
is clocked so that accesses to the two-wire serial interface continue to function correctly.
See “Power Saving Modes” on page 42 for further details.
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
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44
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