2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written.
(www.micronsemi.com/datasheets/syncds.html) for
the latest data sheet.
During WRITE cycles on the x18 device, BWa#
controls DQa pins and DQPa; BWb# controls DQb pins
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
Micron’s 2Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for 486,
Pentium®, 680X0, and PowerPC systems and systems
thatbenefitfromaverywidedatabus. Thedeviceisalso
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please
refer
to
Micron’s
Web
site
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NC/DQPc**
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa**
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
V
SS
V
SS
VDD
Q
V
DD
Q
DQc
NC
NC
NC
DQd
DQd
NC/DQPd**
DQa
NC
NC
SA
DQb
DQb
NC/DQPb**
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
V
V
DD
Q
V
V
DD
Q
SS
SS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
MODE
SA
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
SS
V
V
SS
DD
Q
SA1
SA0
DNU
DNU
DD
Q
DQb
DQb
DQc
DQc
DQa
DQa
ZZ
V
V
SS
CLK
DD
V
SS
V
DD
V
SS
NC
SS
V
DD
NC
SS
VDD
V
DNU
DNU
SA
V
CE2#
BWa#
BWb#
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
V
V
DD
Q
SA
SA
SA
SA
V
V
DD
Q
NC
NC
BWc#
BWd#
SS
SS
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
NC/SA*
SA
*Pin 50 is reserved for address expansion.
**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 6/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000,MicronTechnology,Inc.
3
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