256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
Figure 48: WRITE With Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
Command
DQM
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
t
t
t
t
AH
AS
Address
Row
Row
Bank
Row
Column m
t
AS
AH
Enable auto precharge
Row
A10
t
AS
AH
BA0, BA1
Bank
Bank
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
DIN
DIN
DIN
DQ
t
t
RP
t
RCD
WR
t
RAS
t
RC
Don’t Care
1. For this example, BL = 4.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 1999 Micron Technology, Inc. All rights reserved.
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