256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
Figure 51: Single WRITE Without Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
Command
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
t
CMS CMH
DQM
t
t
AS
AH
Row
Column m
Address
t
t
AS
AH
All banks
Row
Row
A10
Single bank
Bank
Disable auto precharge
Bank
t
t
AH
AS
BA0, BA1
Bank
Bank
t
t
DS DH
DIN
DQ
t
t
t
RCD
WR
RP
t
RAS
t
RC
Don’t Care
1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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