256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
Figure 46: WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
Bank n
READ - AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
Command
Bank n
Interrupt burst, write-back Precharge
t
Page active
WRITE with burst of 4
Internal
States
RP - bank n
t
WR - bank n
t
RP - bank m
Page active
READ with burst of 4
Bank m
Bank n,
Col a
Bank m,
Col d
Address
DQ
DIN
DIN
DOUT
DOUT
CL = 3 (bank m)
Don’t Care
1. DQM is LOW.
Note:
Figure 47: WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
Bank n
WRITE - AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
Command
Bank n
Page active
WRITE with burst of 4
Interrupt burst, write-back Precharge
t
RP - bank n
t
Internal
States
WR - bank n
t
WR - bank m
Write-back
Page active
WRITE with burst of 4
Bank m
Bank n,
Col a
Bank m,
Col d
Address
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
Don’t Care
1. DQM is LOW.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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