256Mb: x4, x8, x16 SDRAM
WRITE Operation
Figure 33: Random WRITE Cycles
T0
T1
T2
T3
CLK
WRITE
WRITE
WRITE
WRITE
Command
Address
DQ
Bank,
Col n
Bank,
Col a
Bank,
Col x
Bank,
Col m
D
D
D
D
IN
IN
IN
IN
Transitioning data
Don’t Care
1. Each WRITE command can be issued to any bank. DQM is LOW.
Note:
Figure 34: WRITE-to-READ
T0
T1
T2
T3
T4
T5
CLK
WRITE
NOP
READ
NOP
NOP
NOP
Command
Address
DQ
Bank,
Col n
Bank,
Col b
DIN
DIN
DOUT
DOUT
Don’t Care
Transitioning data
1. The WRITE command can be issued to any bank, and the READ command can be to any
bank. DQM is LOW. CL = 2 for illustration.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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