256Mb: x4, x8, x16 SDRAM
WRITE Operation
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 16 (page 34).
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 31 (page 59)). A continuous page burst continues until terminated;
at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previ-
ous WRITE command, and the data provided coincident with the new command ap-
plies to the new command (see Figure 32 (page 60)). Data n + 1 is either the last of a
burst of two or the last desired data element of a longer burst.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in Figure 33 (page 61), or each
subsequent WRITE can be performed to a different bank.
Figure 31: WRITE Burst
T0
T1
T2
T3
CLK
WRITE
NOP
NOP
NOP
Command
Address
DQ
Bank,
Col n
DIN
DIN
Transitioning data
1. BL = 2. DQM is LOW.
Don’t Care
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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