256Mb: x4, x8, x16 SDRAM
READ Operation
Figure 30: READ – DQM Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
Command
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
t
CMH
CMS
DQM
t
AS
t
AH
Row
Column m
Address
t
t
AS
AH
Enable auto precharge
Row
A10
Disable auto precharge
Bank
t
AS
t
AH
BA0, BA1
Bank
t
AC
t
t
t
t
t
AC
OH
DOUT
t
AC
OH
OH
DQ
DOUT
DOUT
t
t
LZ
LZ
t
HZ
HZ
t
RCD
CL = 2
Don’t Care
Undefined
1. For this example, BL = 4 and CL = 2.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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