ADVANCE
128Mb: x16, x32
MOBILE SDRAM
ALTERNATING BANK WRITE ACCESSES1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQMU, DQML
A0-A9, A11
t
t
AH
AS
2
2
ROW
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
AS
t
AH
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
D
IN
m
D
IN m + 1
D
IN m + 2
D
IN m + 3
D
IN
b
D
IN b + 1
D
IN b + 2
D
IN b + 3
DQ
t
t
t
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
DON’T CARE
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
MIN
1
MAX
MIN
MAX UNITS
SYMBOL*
MIN
2.5
1
MAX
MIN
2.5
1
MAX UNITS
t
t
t
t
t
t
t
t
t
t
AH
1
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
ns
ns
ns
t
AS
2.5
3
t
CH
DS
2.5
48
2.5
50
t
CL
3
3
RAS
RC
120,000
120,000
ns
ns
ns
ns
ns
–
t
CK (3)
8
10
12
25
1
80
100
20
t
CK (2)
10
20
1
RCD
RP
20
t
CK (1)
20
20
t
CKH
RRD
WR
20
20
t
CKS
2.5
1
2.5
1
1 CLK +
7ns
1 CLK +
5ns
t
CMH
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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