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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
READ Operation  
READ Operation  
READ bursts are initiated with a READ command, as shown in Figure 11 (page 30). The  
starting column and bank addresses are provided with the READ command, and auto  
precharge is either enabled or disabled for that burst access. If auto precharge is ena-  
bled, the row being accessed is precharged at the completion of the burst. In the follow-  
ing figures, auto precharge is disabled.  
During READ bursts, the valid data-out element from the starting column address is  
available following the CAS latency after the READ command. Each subsequent data-  
out element will be valid by the next positive clock edge. Figure 19 (page 49) shows  
general timing for each possible CAS latency setting.  
Upon completion of a burst, assuming no other commands have been initiated, the DQ  
signals will go to High-Z. A continuous page burst continues until terminated. At the  
end of the page, it wraps to column 0 and continues.  
Data from any READ burst can be truncated with a subsequent READ command, and  
data from a fixed-length READ burst can be followed immediately by data from a READ  
command. In either case, a continuous flow of data can be maintained. The first data  
element from the new burst either follows the last element of a completed burst or the  
last desired data element of a longer burst that is being truncated. The new READ com-  
mand should be issued x cycles before the clock edge at which the last desired data ele-  
ment is valid, where x = CL - 1. This is shown in Figure 19 (page 49) for CL2 and CL3.  
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-  
sociated with a prefetch architecture. A READ command can be initiated on any clock  
cycle following a READ command. Full-speed random read accesses can be performed  
to the same bank, or each subsequent READ can be performed to a different bank.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
47  
© 1999 Micron Technology, Inc. All rights reserved.