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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
READ Operation  
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is  
zero clocks for input buffers) to ensure that the written data is not masked. Figure 20  
(page 50) shows where, due to the clock cycle frequency, bus contention is avoided  
without having to add a NOP cycle, while Figure 21 (page 51) shows the case where an  
additional NOP cycle is required.  
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-  
mand to the same bank, provided that auto precharge was not activated. The PRE-  
CHARGE command should be issued x cycles before the clock edge at which the last de-  
sired data element is valid, where x = CL - 1. This is shown in Figure 22 (page 51) for  
each possible CL; data element n + 3 is either the last of a burst of four or the last de-  
sired data element of a longer burst. Following the PRECHARGE command, a subse-  
quent command to the same bank cannot be issued until tRP is met. Note that part of  
the row precharge time is hidden during the access of the last data element(s).  
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-  
mand issued at the optimum time (as described above) provides the same operation  
that would result from the same fixed-length burst with auto precharge. The disadvant-  
age of the PRECHARGE command is that it requires that the command and address  
buses be available at the appropriate time to issue the command. The advantage of the  
PRECHARGE command is that it can be used to truncate fixed-length or continuous  
page bursts.  
Figure 20: READ-to-WRITE  
T0  
T1  
T2  
T3  
T4  
CLK  
DQM  
READ  
NOP  
NOP  
NOP  
Command  
Address  
WRITE  
Bank,  
Col n  
Bank,  
Col b  
t
CK  
t
HZ  
DOUT  
DIN  
DQ  
t
DS  
Transitioning data  
Don’t Care  
1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be  
to any bank. If a burst of one is used, DQM is not required.  
Note:  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
50  
© 1999 Micron Technology, Inc. All rights reserved.  
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