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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Mode Register  
CAS Latency  
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ  
command and the availability of the output data. The latency can be set to two or three  
clocks.  
If a READ command is registered at clock edge n, and the latency is m clocks, the data  
will be available by clock edge n + m. The DQ start driving as a result of the clock edge  
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the  
data is valid by clock edge n + m. For example, assuming that the clock cycle time is  
such that all relevant access times are met, if a READ command is registered at T0 and  
the latency is programmed to two clocks, the DQ start driving after T1 and the data is  
valid by T2.  
Reserved states should not be used as unknown operation or incompatibility with fu-  
ture versions may result.  
Figure 16: CAS Latency  
T0  
T1  
T2  
T3  
CLK  
Command  
READ  
NOP  
NOP  
t
t
OH  
LZ  
D
DQ  
OUT  
t
AC  
CL = 2  
T0  
T1  
T2  
T3  
T4  
CLK  
Command  
READ  
NOP  
NOP  
NOP  
t
t
OH  
LZ  
D
DQ  
OUT  
t
AC  
CL = 3  
Don’t Care  
Undefined  
Operating Mode  
Write Burst Mode  
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-  
nations of values for M7 and M8 are reserved for future use. Reserved states should not  
be used because unknown operation or incompatibility with future versions may result.  
When M9 = 0, the burst length programmed via M[2:0] applies to both READ and  
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but  
write accesses are single-location (nonburst) accesses.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
45  
© 1999 Micron Technology, Inc. All rights reserved.